january 2001 advance information copyright ? alliance semiconductor. all rights reserved. as7c256 as7c3256 1/10/2001 alliance semiconductor p. 1 of 9 5v/3.3v 32k x 8 cmos sram (common i/o) ? features ? as7c256 (5v version) as7c3256 (3.3v version) industrial and commercial temperature organization: 262,144 words 16 bits high speed - 12/15/20 ns address access time - 5/6/7/9 ns output enable access time very low power consumption: active - 660mw (as7c256) / max @ 12 ns - 216mw (as7c3256) / max @ 12 ns very low power consumption: standby - 22 mw (as7c256) / max cmos i/o - 7.2 mw (as7c3256) / max cmos i/o 2.0v data retention easy memory expansion with ce and oe inputs ttl-compatible, three-state i/o 28-pin jedec standard packages -300 mil pdip -300 mil soj -8 13.4 tsop esd protection 2000 volts latch-up current 200 ma logic block diagram a 8 a 7 256 x 128 x 8 array (262,144) input buffer a0 a1 a2 a3 a4 a5 a6 a14 a 9 a 10 a 11 a 12 a 13 i/o0 i/o7 v cc gnd oe ce we column decoder row decoder control circuit sense amp pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 v cc we a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd as7c256 as7c3256 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 v cc we a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd as7c256 as7c3256 16 15 28-pin tsop i (813.4) 28-pin dip, soj (300 mil) note: this part is compatible with both pin numbering conventions used by various manufacturers. (21) (20) (19) (18) (17) (16) (15) (14) (13) (12) (11) (10) (9) (8) (22) (23) (24) (25) (26) (27) (28) (1) (2) (3) (4) (5) (6) (7) selection guide as7c256-10 as7c3256-10 as7c256-12 as7c3256-12 as7c256-15 as7c3256-15 as7c256-20 as7c3256-20 unit maximum address access time 10 12 15 20 ns maximum output enable access time 5 6 7 ns maximum operating current as7c256 120 115 110 ma as7c3256 60 55 50 ma maximum cmos standby current as7c256 4 4 4 ma as7c3256 2 2 2 ma
? as7c256 as7c3256 1/10/2001 alliance semiconductor p. 2 of 9 functional description the as7c(3)256 is a 5v/3.3v high-performance cmos 262,144-bit static random-access memory (sram) device organized as 262,144 words 16 bits. it is designed for memory applications requiring fast data access at low voltage, including pentium tm , powerpc tm , and portable computing. alliance?s advanced circuit design and process techniques permit 3.3v operation without sacrificing performance or operating margins. the device enters standby mode when ce is high. cmos standby mode consumes 3.6 mw. normal operation offers 75% power reduction after initial access, resulting in significant power savings during cpu idle, suspend, and stretch mode. both version s of the as7c256 offer 2.0v data retention. equal address access and cycle times (t aa , t rc , t wc ) of 12/15/20 ns with output enable access times (t oe ) of 5/6/7/9 ns are ideal for high-performance applications. the chip enable ( ce ) input permits easy memory expansion with multiple-bank memory organizations. a write cycle is accomplished by asserting chip enable ( ce ) and write enable ( we ) low. data on the input pins i/o0-i/o7 is written on the rising edge of we (write cycle 1) or ce (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable ( oe ) or write enable ( we ). a read cycle is accomplished by asserting chip enable ( ce ) and output enable ( oe ) low, with write enable ( we ) high. the chip drives i/o pins with the data word referenced by the input address. when chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode. all chip inputs and outputs are ttl-compatible and 5v tolerant. operation is from a single 3.30.3v supply. the as7c(3)256a is packaged in high volume industry standard packages. absolute maximum ratings stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute max- imum rating conditions for extended periods may affect reliability. truth table key: x = don?t care, l = low, h = high parameter device symbol min max unit vo l t ag e o n v cc relative to gnd as7c256 v t1 ?0.5 +7.0 v as7c3256 v t1 ?0.5 +5.0 v voltage on any pin relative to gnd v t2 ?0.5 v cc + 0.5 v power dissipation p d ?1.0w storage temperature (plastic) t stg ?65 +150 o c ambient temperature with v cc applied t bias ?55 +125 o c dc current into outputs (low) i out ?20ma ce we oe data mode h x x high z standby (i sb , i sb1 ) l h h high z output disable (i cc ) lhld out read (i cc ) llxd in write (i cc )
? as7c256 as7c3256 1/10/2001 alliance semiconductor p. 3 of 9 recommended operating conditions * v il min = ?2.0v for pulse width less than t rc /2. dc operating characteristics (over the operating range) 1 capacitance (f = 1mhz, t a = room temperature, v cc = nominal) 2 parameter device symbol min typical max unit supply voltage as7c256 v cc 4.5 5.0 5.5 v as7c3256 v cc 3.0 3.3 3.6 v input voltage as7c256 v ih 2.2 ? v cc +0.5 v as7c3256 v ih 2.0 ? v cc +0.5 v ?v il * -0.5 * ?0.8v ambient operating temperature commercial t a 0?70 o c industrial t a ?40 ? 85 o c parameter sym test conditions device -10 -12 -15 -20 unit min max min max min max min max input leakage current | i li | v cc = max, v in = gnd to v cc ?1?1?1a output leakage current | i lo | v cc = max, v out = gnd to v cc ?1?1?1a operating power supply current i cc v cc = max, ce v il f = f max , i out = 0ma as7c256 ? 120 ? 115 ? 110 ma as7c3256 ?60? 55 ? 50 standby power supply current i sb v cc = max, ce v il f = f max , i out = 0ma as7c256 ?40? 35 ? 30 ma as7c3256 ?20? 20 ? 20 i sb1 v cc = max, ce > v cc ?0.2v v in < gnd + 0.2v or v in > v cc ?0.2v, f = 0 as7c256 ? 4.0 ? 4.0 ? 4.0 ma as7c3256 ? 2.0 ? 2.0 ? 2.0 output voltage v ol i ol = 8 ma, v cc = min ? 0.4 ? 0.4 ? 0.4 v v oh i oh = ?4 ma, v cc = min 2.4 ? 2.4 ? 2.4 ? v parameter symbol signals test conditions max unit input capacitance c in a, ce , we , oe v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf
? as7c256 as7c3256 1/10/2001 alliance semiconductor p. 4 of 9 read cycle (over the operating range) 3,9 key to switching waveforms read waveform 1 (address controlled) 3,6,7,9 read waveform 2 (ce controlled) 3,6,8,9 parameter symbol -10 -12 -15 -20 unit notes min max min max min max min max read cycle time t rc 12 ? 15 ? 20 ? ns address access time t aa ?12?15?20ns 3 chip enable (ce ) access time t ace ?12?15?20ns 3 output enable (oe ) access time t oe ?5?6?7ns output hold from address change t oh 3?3?3?ns 5 ce low to output in low z t clz 3?3?3?ns4, 5 ce high to output in high z t chz ?3?4?5ns4, 5 oe low to output in low z t olz 0?0?0?ns4, 5 oe high to output in high z t ohz ?3?4?5ns4, 5 power up time t pu 0?0?0?ns4, 5 power down time t pd ?12?15?20ns4, 5 undefined output/don?t care falling input rising input address d out data valid t oh t aa t rc supply current ce oe d out t rc 1 t oe t olz t ace t chz t clz t pu t pd i cc i sb 50% 50% t ohz data valid
? as7c256 as7c3256 1/10/2001 alliance semiconductor p. 5 of 9 write cycle (over the operating range) 11 shaded areas contain advance information. write waveform 1 (we controlled) 10,11 write waveform 2 (ce controlled) 10,11 parameter symbol -10 -12 -15 -20 unit notes min max min max min max write cycle time t wc 12 ? 15 ? 20 ? ns chip enable to write end t cw 8?10?12? ns address setup to write end t aw 8?10?12? ns address setup time t as 0?0?0? ns write pulse width t wp 8?9?12? ns address hold from end of write t ah 0?0?0? ns data valid to write end t dw 6?8?10? ns data hold time t dh 0?0?0? ns4, 5 write enable to output in high z t wz ?5?5?5 ns4, 5 output active from write end t ow 3?3?3? ns4, 5 t aw t ah t wc address we d in d out t dh t ow t dw t wz t wp t as data valid t aw address ce we d in d out data valid t cw t wp t dw t dh t ah t wz t wc t as
? as7c256 as7c3256 1/10/2001 alliance semiconductor p. 6 of 9 data retention characteristics (over the operating range) 13 data retention waveform ac test conditions notes 1during v cc power-up, a pull-up resistor to v cc on ce is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions , figures a, b, c. 4 these parameters are specified with cl = 5pf, as in figures b or c. transition is measured 500mv from steady-state voltage. 5 this parameter is guaranteed, but not tested. 6we is high for read cycle. 7ce and oe are low for read cycle. 8 address valid prior to or coincident with ce transition low. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 ce or we must be high during address transitions. either ce or we asserting high terminates a write cycle. 11 all write cycle timings are referenced from the last valid address to the first transitioning address. 12 ce1 and ce2 have identical timing. 13 2v data retention applies to the commercial operating range only. 14 c=30pf, except on high z and low z parameters, where c=5pf. parameter symbol test conditions min max unit v cc for data retention v dr v cc = 2.0v ce v cc ?0.2v v in v cc ?0.2v or v in 0.2v 2.0 ? v data retention current i ccdr ?500a ??a chip enable to data retention time t cdr 0?ns operation recovery time t r t rc ?ns input leakage current | i li | ?1a v cc ce t r t cdr data retention mode vcc vcc v dr 2.0v v ih v ih v dr 350 ? c(14) 320 ? d out gnd +3.3v 168 ? d out +1.72v (5v and 3.3v) figure c: output load 255 ? c(14) 480 ? d out gnd +5v figure b: output lo ad thevenin equivalent - output load: see figure b or figure c. - input pulse level: gnd to 3.0v. see figure a. - input rise and fall times: 2 ns. see figure a. - input and output timing reference levels: 1.5v. 10% 90% 10% 90% gnd +3.0v figure a: input pulse 2 ns
? as7c256 as7c3256 1/10/2001 alliance semiconductor p. 7 of 9 typical dc and ac characteristics supply voltage (v) min max nominal 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb ambient temperature (c) ?55 80 125 35 ?10 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb vs. ambient temperature t a vs. supply voltage v cc i cc i sb i cc i sb ambient temperature (c) -55 80 125 35 -10 0.2 1 0.04 5 25 625 normalized i sb1 (log scale) normalized supply current isb1 vs. ambient temperature t a v cc = v cc (nominal) supply voltage (v) min max nominal 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa ambient temperature (c) ?55 80 125 35 ?10 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa cycle frequency (mhz) 075 100 50 25 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc normalized supply current i cc vs. ambient temperature t a vs. cycle frequency 1/t rc , 1/t wc vs. supply voltage v cc v cc = v cc (nominal) t a = 25c v cc = v cc (nominal) t a = 25c output voltage (v) v cc 0 20 60 80 40 100 120 140 output source current (ma) output source current i oh output voltage (v) v cc output sink current (ma) output sink current i ol vs. output voltage v ol vs. output voltage v oh 0 20 60 80 40 100 120 140 v cc = v cc (nominal)pl t a = 25c v cc = v cc (nominal) t a = 25c capacitance (pf) 0 750 1000 500 250 0 5 15 20 10 25 30 35 change in t aa (ns) typical access time change ? t aa vs. output capacitive loading v cc = v cc(nominal) 00
? as7c256 as7c3256 1/10/2001 alliance semiconductor p. 8 of 9 package diagrams c ea seating b a1 e1 e d e l s plane b a pin 1 28-pin pdip min max a - 0.175 a1 0.010 - b 0.058 0.064 b 0.016 0.022 c 0.008 0.014 d - 1.400 e 0.295 0.320 e1 0.278 0.298 e0.100 bsc ea 0.330 0.370 l 0.120 0.140 0 15 s - 0.055 28-pin soj min max a - 0.140 a1 0.025 - a2 0.095 0.105 b 0.028 typ b 0.018 typ c 0.010 typ d - 0.730 e 0.245 0.285 e1 0.295 0.305 e2 0.327 0.347 e 0.050 bsc 28-pin 813.4 min max a ?1.20 a1 0.10 0.20 a2 0.95 1.05 b 0.15 0.25 c 0.10 0.20 d 11.60 11.80 e 0.55 nominal e d e1 pin 1 b b a1 a2 c e seating plane e2 a e b e hd d c l a1 a a2 28-pin pin 8(21) pin 1(7) pin 5(8) pin 1(22) note: this part is compatible with both pin numbering conventions used by various manufacturers.
? copyright alliance semiconductor corporation. all rights reserved. our three-point logo, our name and intelliwatt are tradema rks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its produ cts at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance?s best data and/or estimates at the time of iss uance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the inf ormation in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or cus tomer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a par- ticular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance? s terms and conditions of sale (which are available from alliance). all sales of alli- ance products are made exclusively according to alliance?s terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its pro ducts for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. ? as7c256 as7c3256 1/10/2001 alliance semiconductor p. 9 of 9 ordering information part numbering system package / access time volt/temp 10 ns 12 ns 15 ns 20 ns plastic dip, 300 mil 5v commercial as7c256-10pc as7c256-12pc as7c256-15pc as7c256-20pc 3.3v commercial as7c3256-10pc as7c3256-12pc as7c3256-15pc as7c3256-20pc plastic soj, 300 mil 5v commercial as7c256-10jc as7c256-12jc as7c256-15jc as7c256-20jc 3.3v commercial as7c3256-10jc as7c3256-12jc as7c3256-15jc as7c3256-20jc 5v industrial as7c256-10ji as7c256-12ji as7c256-15ji as7c256-20ji 3.3v industrial as7c3256-10ji as7c3256-12ji as7c3256-15ji as7c3256-20ji tsop 8x13.4 5v commercial as7c256-10tc as7c256-12tc as7c256-15tc as7c256-20tc 3.3v commercial as7c3256-10tc AS7C3256-12TC as7c3256-15tc as7c3256-20tc 5v industrial as7c256-10ti as7c256-12ti as7c256-15ti as7c256-20ti 3.3v industrial as7c3256-10ti as7c3256-12ti as7c3256-15ti as7c3256-20ti as7c 3 256 ?xx x c or i sram prefix 3 = 3.3v supply device number access time package: j = soj 300 mil t = tsop 8x13.4 commercial temperature range: 0 o c to 70 0 c industrial temperature range: -40c to 85c
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